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DS1986 64k bit addonly i button tm DS1986 3.10 ground data 0.36 0.51 5.89 ground data 0.36 0.51 all dimensions shown in millimeters. f3 microcan tm f5 microcan tm 0f 99 000000fbd8b3 yyww 16.25 17.35 registered rr 0f 19 000000fbc52b yyww 16.25 17.35 registered rr 052298 1/24 special features ? 65536bits electrically programmable read only memory (eprom) communicates with the economy of one signal plus ground ? overdrive mode boosts communication speed to 142k bits per second ? eprom partitioned into two hundred and fiftysix 256bit pages for randomly accessing packetized data records ? each memory page can be permanently writepro- tected to prevent tampering ? device is an aadd onlyo memory where additional data can be programmed into eprom without disturbing existing data ? architecture allows software to patch data by super- seding an old page in favor of a newly programmed page ? reduces control, address, data, power, and program- ming signals to a single data pin ? 8bit family code specifies DS1986 communications requirements to reader ? reads over a wide voltage range of 2.8v to 6.0v from 40 c to +85 c; programs at 11.5v to 12.0v from 40 c to +85 c common i button features ? unique, factorylasered and tested 64bit registra- tion number (8bit family code + 48bit serial number + 8bit crc tester) assures absolute traceability because no two parts are alike ? multidrop controller for microlan tm ? digital identification and information by momentary contact ? chipbased data carrier compactly stores information ? data can be accessed while affixed to object ? economically communicates to bus master with a single digital signal at 16.3k bits per second ? standard 16 mm diameter and 1wire tm protocol ensure compatibility with i button family ? button shape is selfaligning with cupshaped probes ? durable stainless steel case engraved with registra- tion number withstands harsh environments ? easily affixed with selfstick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim ? presence detector acknowledges when reader first applies voltage ? meets ul#913 (4th edit.); intrinsically safe appara- tus, approved under entity concept for use in class i, division 1, group a, b, c and d locations (applica- tion pending)
DS1986 052298 2/24 ordering information DS1986f3 f3 microcan DS1986f5 f5 microcan examples of accessories ds9096p selfstick adhesive pad ds9101 multipurpose clip ds9093ra mounting lock ring ds9093f snapin fob ds9092 i button probe i button description the DS1986 64k bit addonly i button is a rugged read/ write data carrier that identifies and stores relevant information about the product or person to which it is attached. this information can be accessed with mini- mal hardware, for example a single port pin of a micro- controller. the DS1986 consists of a factorylasered registration number that includes a unique 48bit serial number, an 8bit crc, and an 8bit family code (0fh) plus 64k bit of eprom which is userprogrammable. the power to program and read the DS1986 is derived entirely from the 1wire communication line. data is transferred serially via the 1wire protocol which requires only a single data lead and a ground return. the entire device can be programmed and then writepro- tected if desired. alternatively, the part may be pro- grammed multiple times with new data being appended to, but not overwriting, existing data with each subse- quent programming of the device. note: individual bits can be changed only from a logical 1 to a logical 0, never from a logical 0 to a logical 1. a provision is also included for indicating that a certain page or pages of data are no longer valid and have been replaced with new or updated data that is now residing at an alternate page address. this page address redirection allows software to patch data and enhance the flexibility of the device as a standalone database. the 48bit serial number that is factorylasered into each DS1986 provides a guaran- teed unique identity which allows for absolute traceabil- ity. the durable microcan package is highly resistant to harsh environments such as dirt, moisture, and shock. its compact buttonshaped profile is selfaligning with cupshaped receptacles, allowing the DS1986 to be used easily by human operators or automatic equipment. accessories permit the DS1986 to be mounted on printed circuit boards, plastic key fobs, photoid badges, id bracelets, and many other objects. applications include workinprogress tracking, electronic travelers, access control, storage of calibration constants, and debit tokens. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the DS1986. the DS1986 has three main data compo- nents: 1) 64bit lasered rom, 2) 65536 bits eprom data memory, and 3) 2816 bits eprom status memory. the device derives its power for read operations entirely from the 1wire communication line by storing energy on an internal capacitor during periods of time when the signal line is high and continues to operate off of this aparasiteo power source during the low times of the 1wire line until it returns high to replenish the parasite (capacitor) supply. during programming, 1wire com- munication occurs at normal voltage levels and then is pulsed momentarily to the programming voltage to cause the selected eprom bits to be programmed. the 1wire line must be able to provide 12 volts and 10 mil- liamperes to adequately program the eprom portions of the part. whenever programming voltages are pres- ent on the 1wire line a special high voltage detect cir- cuit within the DS1986 generates an internal logic signal to indicate this condition. the hierarchical structure of the 1wire protocol is shown in figure 2. the bus mas- ter must first provide one of the six rom function com- mands, 1) read rom, 2) match rom, 3) search rom, 4) skip rom, 5) overdrive-skip rom, or 6) overdrive- match rom. upon completion of an overdrive rom command byte executed at regular speed, the device will enter the overdrive mode where all subsequent communication occurs at a higher speed. these com- mands operate on the 64bit lasered rom portion of each device and can singulate a specific device if many are present on the 1wire line as well as indicate to the bus master how many and what types of devices are present. the protocol required for these rom function commands is described in figure 8. after a rom func- tion command is successfully executed, the memory functions that operate on the eprom portions of the DS1986 become accessible and the bus master may issue any one of the five memory function commands specific to the DS1986 to read or program the various data fields. the protocol for these memory function commands is described in figure 5. all data is read and written least significant bit first. 64bit lasered rom each DS1986 contains a unique rom code that is 64 bits long. the first eight bits are a 1wire family code. the next 48 bits are a unique serial number. the last eight bits are a crc of the first 56 bits. (see figure 3.)
parasite power 1wire function control 64bit lasered rom program voltage detect memory function control 8bit scratchpad 16bit crc generator 64k bit eprom (256 pages of 32 bytes) 352 eprom status bytes data 1wire bus DS1986 052298 3/24 the 64bit rom and rom function control section allow the DS1986 to operate as a 1wire device and fol- low the 1wire protocol detailed in the section a1wire bus systemo. the memory functions required to read and program the eprom sections of the DS1986 are not accessible until the rom function protocol has been satisfied. this protocol is described in the rom func- tions flow chart (figure 8). the 1wire bus master must first provide one of six rom function commands: 1) read rom, 2) match rom, 3) search rom, or 4) skip rom, 5) overdrive-skip rom, or 6) overdrivematch rom. after a rom function sequence has been suc- cessfully executed, the bus master may then provide any one of the memory function commands specific to the DS1986 (figure 5). the 1wire crc of the lasered rom is generated using the polynomial x 8 + x 5 + x 4 + 1. additional information about the dallas semiconductor 1wire cyclic redun- dancy check is available in the book of ds19xx i button standards. the shift register acting as the crc accu- mulator is initialized to zero. then starting with the least significant bit of the family code, one bit at a time is shifted in. after the eighth bit of the family code has been entered, then the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. shifting in the eight bits of crc should return the shift register to all zeroes. DS1986 block diagram figure 1
DS1986 052298 4/24 hierarchical structure for 1wire protocol figure 2 1wire rom function commands (see figure 9) DS1986 specific memory function commands (see figure 6) command level: available commands: data field affected: read rom match rom search rom skip rom 64bit rom 64bit rom 64bit rom n/a write memory 64k bit eprom write status read memory read status extended read data eprom status bytes 64k bit eprom eprom status bytes 64k bit eprom bus master 1wire bus other devices DS1986 overdrive skip rom overdrive match rom n/a 64bit rom 64bit lasered rom figure 3 8bit crc code 48bit serial number 8bit family code (0fh) msb lsb msb lsb msb lsb
DS1986 052298 5/24 65536bits eprom the memory map in figure 4 shows the 65536bit eprom section of the DS1986 which is configured as 256 pages of 32 bytes each. the 8bit scratchpad is an additional register that acts as a buffer when program- ming the memory. data is first written to the scratchpad and then verified by reading an 16bit crc from the DS1986 that confirms proper receipt of the data and address. if the buffer contents are correct, a program- ming voltage should be applied and the byte of data will be written into the selected address in memory. this process insures data integrity when programming the memory. the details for reading and programming the 65536bit eprom portion of the DS1986 are given in the memory function commands section. eprom status bytes in addition to the 65536 bits of data memory the DS1986 provides 2816 bits of status memory accessible with separate commands. the eprom status bytes can be read or programmed to indicate various conditions to the software interrogat- ing the DS1986. the first 32 bytes of the eprom status memory (addresses 000 to 01fh) contain the write pro- tect page bits which inhibit programming of the corre- sponding page in the 65536bit main memory area if the appropriate write protection bit is programmed. once a bit has been programmed in the write protect page sec- tion of the status memory, the entire 32 byte page that corresponds to that bit can no longer be altered but may still be read. the next 32 bytes of the eprom status memory (addresses 020 to 03fh) contain the write protect bits which inhibit altering the page address redirection byte corresponding to each page in the 65536bit main memory area. the following 32 bytes within the eprom status memory (addresses 040 to 05fh) are reserved for use by the i button operating software tmex. their purpose is to indicate which memory pages are already in use. originally, all of these bits are unprogrammed, indicat- ing that the device does not store any data. as soon as data is written to any page of the device under control of tmex, the bit inside this bitmap corresponding to that page will be programmed to 0, marking this page as used. these bits are application flags only and have no impact on the internal logic of the DS1986. the next 256 bytes of the eprom status memory (addresses 100h to 1ffh) contain the page address redirection bytes which indicate if one or more of the pages of data in the 65536bit eprom section have been invalidated by software and redirected to the page address contained in the appropriate redirection byte. the hardware of the DS1986 makes no decisions based on the contents of the page address redirection bytes. since with eprom technology bits can only be changed from a logical 1 to a logical 0 by programming, it is not possible to simply rewrite a page if the data requires changing or updating. but with space permit- ting, an entire page of data can be redirected to another page within the DS1986. under tmex a page is redi- rected by writing the one's complement of the new page address into the page address redirection byte that corresponds to the original (replaced) page. this archi- tecture allows the user's software to make a adata patcho to the eprom by indicating that a particular page or pages should be replaced with those indicated in the page address redirection bytes. to leave an authentic audit trail of data patches, it is recommended to also program the write protect bit of the page address redirection byte, after the page redirection is pro- grammed. without this protection, it is still possible to modify the page address redirection byte, making it point to a different memory page than the true one. if a page address redirection byte has a ffh value, the data in the main memory that corresponds to that page is valid. if a page address redirection byte has some other hex value than ffh, the data in the page corre- sponding to that redirection byte is invalid. according to the tmex definitions the valid data can now be found at the one's complement of the page address indicated by the hex value stored in the associated page address redirection byte. a value of fdh in the redirection byte for page 1, for example, would indicate that the updated data is now in page 2. the status memory is pro- grammed similarly to the data memory. details for read- ing and programming the eprom status memory por- tion of the DS1986 are given in the memory function commands section. the status memory address range of the DS1986 extends from 000 to 1ffh. the memory locations 60h to 0ffh and 200h and higher are physically not imple- mented. reading these locations will usually result in ffh bytes. attempts to write to these locations will be ignored.
DS1986 052298 6/24 DS1986 memory map figure 4 32byte final storage eprom page 0 page 1 page 255 8bit redirection bit map of used pages writeprotect bits redirection bytes writeprotect bits data memory 325 bytes status memory scratchpad starting address 0000h 0020h 0040h 1fe0h 64k bit eprom 32byte final storage eprom 32byte final storage eprom bytes status memory map 000h 01fh 020h 03fh 040h 05fh 060h 0ffh 100h 1ffh 44 pages of 8 bytes each 8 bytes writeprotect bits data memory writeprotect bits of redirection bytes bit map of used pages reserved for future extensions redirection bytes ? ? ? ? bit 0 of address 000h=writeprotect of page 0, etc. address 100h=page address redirection byte for page 0, etc.
DS1986 052298 7/24 memory function commands the amemory function flow charto (figure 5) describes the protocols necessary for accessing the various data fields within the DS1986. the memory function control section, 8bit scratchpad, and the program voltage detect circuit combine to interpret the commands issued by the bus master and create the correct control signals within the device. a threebyte protocol is issued by the bus master. it is comprised of a command byte to determine the type of operation and two address bytes to determine the specific starting byte location within a data field. the command byte indicates if the device is to be read or written. writing data involves not only issuing the correct command sequence but also providing a 12volt programming voltage at the appropriate times. to execute a write sequence, a byte of data is first loaded into the scratchpad and then pro- grammed into the selected address. write sequences always occur a byte at a time. to execute a read sequence, the starting address is issued by the bus master and data is read from the part beginning at that initial location and continuing to the end of the selected data field or until a reset sequence is issued. all bits transferred to the DS1986 and received back by the bus master are sent least significant bit first. read memory [f0h] the read memory command is used to read data from the 65536bits eprom data field. the bus master fol- lows the command byte with a two byte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. with every subse- quent read data time slot the bus master receives data from the DS1986 starting at the initial address and con- tinuing until the end of the 65536bits data field is reached or until a reset pulse is issued. if reading occurs through the end of memory space, the bus mas- ter may issue sixteen additional read time slots and the DS1986 will respond with a 16bit crc of the com- mand, address bytes and all data bytes read from the initial starting byte through the last byte of memory. this crc is the result of clearing the crc generator and then shifting in the command byte followed by the two address bytes and the data bytes beginning at the first addressed memory location and continuing through to the last byte of the eprom data memory. after the crc is received by the bus master, any subsequent read time slots will appear as logical 1s until a reset pulse is issued. any reads ended by a reset pulse prior to reaching the end of memory will not have the 16bit crc available. typically a 16bit crc would be stored with each page of data to insure rapid, errorfree data transfers that eliminate having to read a page multiple times to deter- mine if the received data is correct or not. (see book of ds19xx i button standards, chapter 7 for the recom- mended file structure to be used with the 1wire envi- ronment.) if crc values are imbedded within the data, a reset pulse may be issued at the end of memory space during a read memory command. read status [aah] the read status command is used to read data from the eprom status data field. the bus master follows the command byte with a two byte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. with every subse- quent read data time slot the bus master receives data from the DS1986 starting at the supplied address and continuing until the end of an eightbyte page of the eprom status data field is reached. at that point the bus master will receive a 16bit crc of the command byte, address bytes and status data bytes. this crc is computed by the DS1986 and read back by the bus master to check if the command word, starting address and data were received correctly. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. note that the initial pass through the read status flow chart will generate a 16bit crc value that is the result of clearing the crc generator and then shifting in the command byte followed by the two address bytes, and finally the data bytes beginning at the first addressed memory location and continuing through to the last byte of the addressed eprom status data page. the last byte of a status data page always has an ending address of xx7 or xxfh. subsequent passes through the read status flow chart will generate a 16bit crc that is the result of clearing the crc generator and then shifting in the new data bytes starting at the first byte of the next page of the eprom status data field. this feature is provided since the eprom status information may change over time making it impossible to program the data once and include an accompanying crc that will always be valid. therefore, the read sta- tus command supplies a 16bit crc that is based on and always is consistent with the current data stored in the eprom status data field.
f0h read memory ? n bus master t x ta1 (t7:t0) bus master t x ta2 (t15:t8) DS1986 sets memory address = (t15:t0) y bus master r x data from data memory bus master t x reset ? end of data memory ? DS1986 increments address counter aah read status ? bus master t x ta1 (t7:t0) bus master t x ta2 (t15:t8) DS1986 sets status address = (t15:t0) bus master r x data from status memory bus master t x reset ? end of page ? bus master r x crc16 of command, address, data bus master t x reset ? bus master r x 1's DS1986 increments address counter y y n y n y n y y n n y n bus master t x reset ? n bus master r x crc16 of command, address, data (1st pass) crc16 of data (subsequent passes) bus master t x reset ? bus master r x 1's y n end of status memory ? n y y master t x memory function command y crc correct ? bus master t x reset n y to rom functions flow chart (figure 8) 1) 1) 1) 1) 1) 2) 2) 2) 1) 1) 1) 2) 2) 1) 2) 1) 1) from rom functions flow chart (figure 8) DS1986 clears crc generator 1), 2) see next page to figure 5 second part DS1986 052298 8/24 memory function flow chart figure 5
bus master t x reset a5h extended read memory ? n bus master t x ta1 (t7:t0) bus master t x ta2 (t15:t8) DS1986 sets memory address = (t15:t0) y bus master r x redir. byte crc correct ? DS1986 increments address counter y n bus master r x data from data memory bus master t x reset ? end of page ? bus master r x crc16 of preceding page of data end of memory ? bus master t x reset ? bus master r x 1's y n n y n y y n DS1986 increments address counter to write commands legend: decision made by the master decision made by DS1986 bus master r x crc16 of command, address, redir. byte (1st pass) crc16 of redir. byte (subsequent passes) bus master t x reset crc correct ? n 1) to be transmitted or received at overdrive speed if od=1 2) reset pulse to be transmitted at overdrive speed if od=1; reset pulse to be transmitted at regular speed if od=0 or if the DS1986 is to be reset from overdrive speed to regular speed 1) 1) 1) 1) 1) 1) 1) 2) 2) 2) 2) to rom functions flow chart (figure 8) from figure 5 first part DS1986 052298 9/24 memory function flow chart (cont'd) figure 5
DS1986 052298 10/24 memory function flow chart (cont'd) figure 5 0fh write memory ? n bus master t x ta1 (t7:t0) bus master t x ta2 (t15:t8) bus master r x crc16 of command, address, data (1 st pass) crc16 of address, data (subsequent passes) crc correct ? y bus master t x data byte (d7:d0) bus master t x program pulse bus master r x byte from eprom end of data memory ? DS1986 increments address counter DS1986 loads new address into crc generator master t x reset 55h write status ? bus master t x ta1 (t7:t0) bus master t x ta2 (t15:t8) crc correct ? bus master t x data byte (d7:d0) bus master t x program pulse bus master r x byte from eprom master t x reset n y y n n y n y y eprom byte correct ? end of status memory ? DS1986 increments address counter DS1986 loads new address into crc generator y n y eprom byte correct ? bus master r x crc16 of command, address, data (1 st pass) crc16 of address, data (subsequent passes) n n bus master t x reset DS1986 copies scratchpad to status eprom DS1986 copies scratchpad to data eprom 1) 1) 1) 1) 1) 1) 1) 1) 2) 1) 1) 2) 2) to rom functions flow chart (figure 8) 1), 2) see previous page from figure 5 second part
DS1986 052298 11/24 after the 16bit crc of the last eprom status data page is read, the bus master will receive logical 1s from the DS1986 until a reset pulse is issued. the read sta- tus command sequence can be ended at any point by issuing a reset pulse. extended read memory [a5h] the extended read memory command supports page redirection when reading data from the 65536bit eprom data field. one major difference between the extended read memory and the basic read memory command is that the bus master receives the redirec- tion byte first before investing time in reading data from the addressed memory location. this allows the bus master to quickly decide whether to continue and access the data at the selected starting page or to termi- nate and restart the reading process at the redirected page address. a nonredirected page is identified by a redirection byte with a value of ffh (see description of eprom status bytes). if the redirection byte is differ- ent than this, the master has to complement it to obtain the new page number. multiplying the page number by 32 (20h) results in the new address the master has to send to the DS1986 to read the updated data replacing the old data. there is no logical limitation in the number of redirections of any page. the only limit is the number of available memory pages within the DS1986. in addition to page redirection, the extended read memory command also supports abitorientedo applica- tions where the user cannot store a 16bit crc with the data itself. with bitoriented applications the eprom information may change over time within a page bound- ary making it impossible to include an accompanying crc that will always be valid. therefore, the extended read memory command concludes each page with the DS1986 generating and supplying a 16bit crc that is based on and therefore always consistent with the cur- rent data stored in each page of the 65536bit eprom data field. after having sent the command code of the extended read memory command, the bus master follows the command byte with a two byte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. by sending eight read data time slots, the master receives the redirection byte associated with the page given by the starting address. with the next sixteen read data time slots, the bus mas- ter receives a 16bit crc of the command byte, address bytes and the redirection byte. this crc is computed by the DS1986 and read back by the bus master to check if the command word, starting address and redirection byte were received correctly. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is cor- rect, the bus master issues read time slots and receives data from the DS1986 starting at the initial address and continuing until the end of a 32byte page is reached. at that point the bus master will send sixteen additional read time slots and receive a 16bit crc that is the result of shifting into the crc generator all of the data bytes from the initial starting byte to the last byte of the current page. with the next 24 read data time slots the master will receive the redirection byte of the next page followed by a 16bit crc of the redirection byte. after this, data is again read from the 65536bit eprom data field starting at the beginning of the new page. this sequence will continue until the final page and its accompanying crc are read by the bus master. the extended read memory command provides a 16bit crc at two locations within the transaction flow chart: 1) after the redirection byte and 2) at the end of each memory page. the crc at the end of the memory page is always the result of clearing the crc generator and shifting in the data bytes beginning at the first addressed memory location of the eprom data page until the last byte of this page. with the initial pass through the extended read memory flow chart the 16bit crc value is the result of shifting the command byte into the cleared crc generator, followed by the two address bytes and the redirection byte. subsequent passes through the extended read memory flow chart will generate a 16bit crc that is the result of clearing the crc generator and then shifting in the redirection byte only. after the 16bit crc of the last page is read, the bus master will receive logical 1s from the DS1986 until a reset pulse is issued. the extended read memory command sequence can be exited at any point by issu- ing a reset pulse.
DS1986 052298 12/24 writing eprom memory the DS1986 has two independent eprom memory fields, data memory and status memory. the function flow for writing either field is almost identical. after the appropriate write command has been issued, the bus master will send a twobyte starting address (ta1=(t7:t0), ta2=(t15:t8)) and a byte of data (d7:d0). a 16bit crc of the command byte, address bytes, and data byte is computed by the DS1986 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is cor- rect, a programming pulse (12 volts on the 1wire bus for 480 m s) is issued by the bus master. prior to program- ming, the entire eprom memory field will appear as logical 1s. for each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the eprom memory is pro- grammed to a logical 0 after the programming pulse has been applied. after the 480 m s programming pulse is applied and the data line returns to the idle level (5 volts), the bus master issues eight read time slots to verify that the appropriate bits have been programmed. the DS1986 responds with the data from the selected eprom address sent least significant bit first. this byte contains the bitwise logical and of all data ever written to this address. if the eprom byte contains 1s in bit positions where the byte issued by the master contained 0s, a reset pulse should be issued and the current byte address should be programmed again. if the DS1986 eprom byte con- tains 0s in the same bit positions as the data byte, the programming was successful and the DS1986 will auto- matically increment its address counter to select the next byte in the eprom memory field. the new two byte address will also be loaded into the 16bit crc generator as a starting value. the bus master will issue the next byte of data using eight write time slots. as the DS1986 receives this byte of data into the scratchpad, it also shifts the data into the crc genera- tor that has been preloaded with the current address and the result is a 16bit crc of the new data byte and the new address. after supplying the data byte, the bus master will read this 16bit crc from the DS1986 with sixteen read time slots to confirm that the address incremented properly and the data byte was received correctly. if the crc is incorrect, a reset pulse must be issued and the write sequence must be restarted. if the crc is correct, the bus master will issue a programming pulse and the selected byte in memory will be pro- grammed. note that the initial pass through the write flow chart will generate an 16bit crc value that is the result of shift- ing the command byte into the crc generator, followed by the two address bytes, and finally the data byte. sub- sequent passes through the write flow chart due to the DS1986 automatically incrementing its address counter will generate a 16bit crc that is the result of loading (not shifting) the new (incremented) address into the crc generator and then shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the DS1986) is made entirely by the bus master, since the DS1986 will not be able to determine if the 16bit crc calculated by the bus mas- ter agrees with the 16bit crc calculated by the DS1986. if an incorrect crc is ignored and a program pulse is applied by the bus master, incorrect program- ming could occur within the DS1986. also note that the DS1986 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected eprom byte. the decision to continue is again made entirely by the bus master. therefore if the eprom data byte does not match the supplied data byte but the master contin- ues with the write command, incorrect programming could occur within the DS1986. the write command sequence can be ended at any point by issuing a reset pulse.
DS1986 052298 13/24 write memory [0fh]/speed write memory [f3h] the write memory command is used to program the 65536bit eprom data field. the details of the func- tional flow chart are described in the section awriting eprom memoryo. the data memory address range is 0000h to 1fffh. if the bus master sends a starting address higher than this, the three most significant address bits are set to zeros by the internal circuitry of the chip. this will result in a mismatch between the crc calculated by the DS1986 and the crc calculated by the bus master, indicating an error condition. to save time when writing more than one consecutive byte of the DS1986's data memory it is possible to omit reading the 16bit crc which allows verification of data and address before the data is copied to the eprom memory. at regular speed this saves 16 time slots or 976 m s for every byte to be programmed. this speed programming mode is accessed with the command code f3h instead of 0fh. it follows basically the same flow chart as the write memory command, but skips sending the crc immediately preceding the program pulse. this command should only be used if the electri- cal contact between bus master and the DS1986 is firm since a poor contact may result in corrupted data inside the eprom memory. write status [55h]/ speed write status [f5h] the write status command is used to program the 2816bit eprom status memory field. the details of the functional flow chart are described in the section awriting eprom memoryo. the status memory address range is 0000h to 01ffh. attempts to write to the not implemented status memory locations will be ignored. if the bus master sends a start- ing address higher than 1fffh, the three most signifi- cant address bits are set to zeros by the internal circuitry of the chip. this will result in a mismatch between the crc calculated by the DS1986 and the crc calculated by the bus master, indicating an error condition. to save time when writing more than one consecutive byte of the DS1986's status memory it is possible to omit reading the 16bit crc which allows verification of data and address before the data is copied to the eprom memory. at regular speed this saves 16 time slots or 976 m s for every byte to be programmed. this speed programming mode is accessed with the command code f5h instead of 55h. it follows basically the same flow chart as the write status command, but skips send- ing the crc immediately preceding the program pulse. this command should only be used if the electrical con- tact between bus master and the DS1986 is firm since a poor contact may result in corrupted data inside the eprom status memory. 1wire bus system the 1wire bus is a system which has a single bus mas- ter and one or more slaves. in all instances, the DS1986 is a slave device. the bus master is typically a micro- controller. the discussion of this bus system is broken down into three topics: hardware configuration, transac- tion sequence, and 1wire signalling (signal type and timing). a 1wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. for a more detailed protocol description, refer to chapter 4 of the book of ds19xx i button standards. hardware configuration the 1wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1wire bus must have an open drain connection or 3state outputs. the DS1986 is an open drain part with an internal circuit equivalent to that shown in figure 6. the bus master can be the same equivalent circuit. if a bidirectional pin is not available, separate output and input pins can be tied together. the bus master requires a pullup resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in figures 7a and 7b. the value of the pullup resistor should be approximately 5k w for short line lengths.
DS1986 052298 14/24 a multidrop bus consists of a 1wire bus with multiple slaves attached. at regular speed the 1wire bus has a maximum data rate of 16.3k bits per second. the speed can be boosted to 142k bits per second by activating the overdrive mode. if the bus master is also required to perform programming of the eprom portions of the DS1986, a programming supply capable of delivering up to 10 milliamps at 12 volts for 480 m s is required. the idle state for the 1wire bus is high. if, for any reason, a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16 m s (overdrive speed) or more than 120 m s (regular speed), one or more of the devices on the bus may be reset. transaction sequence the sequence for accessing the DS1986 via the 1wire port is as follows: ? initialization ? rom function command ? memory function command ? read/write memory/status initialization all transactions on the 1wire bus begin with an initial- ization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the DS1986 is on the bus and is ready to operate. for more details, see the a1wire signallingo section. rom function commands once the bus master has detected a presence, it can issue one of the six rom function commands. all rom function commands are eight bits long. a list of these commands follows (refer to flowchart in figure 8): read rom [33h] this command allows the bus master to read the DS1986's 8bit family code, unique 48bit serial num- ber, and 8bit crc. this command can be used only if there is a single DS1986 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wiredand result). the resultant family code and 48bit serial number will usually result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64bit rom sequence, allows the bus master to address a specific DS1986 on a multidrop bus. only the DS1986 that exactly matches the 64bit rom sequence will respond to the subsequent memory function command. all slaves that do not match the 64bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. skip rom [cch] this command can save time in a single drop bus sys- tem by allowing the bus master to access the memory functions without providing the 64bit rom code. if more than one slave is present on the bus and a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wiredand result). search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1wire bus or their 64bit rom codes. the search rom com- mand allows the bus master to use a process of elimina- tion to identify the 64bit rom codes of all slave devices on the bus. the rom search process is the repetition of a simple 3step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, 3step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be identified by additional passes. see chapter 5 of the book of ds19xx i button standards for a comprehensive discussion of a rom search, including an actual exam- ple.
DS1986 052298 15/24 DS1986 equivalent circuit figure 6 5 m a typ. 100 w mosfet t x r x data ground bus master circuit figure 7 bus master v dd ttlequivalent port pins 5k w b) standard ttl v dd 5k w programming pulse 12v (10 ma min.) to data connection of DS1986 bus master v dd v dd ds5000 or 8051 equivalent open drain port pin r x t x a) open drain 12v to data connection of DS1986 5k w 10k w 10k w pgm d s d s s d d s 2n7000 2n7000 2n7000 470 pf vp0300l or vp0106n3 or bss110 capacitor added to reduce coupling on data line due to programming signal switching r x t x
n y y y DS1986 t x presence pulse 33h read rom command 55h match rom command f0h search rom command cch skip rom command DS1986 t x family code 1 byte bit 0 match? bit 0 match? bit 1 match? bit 1 match? bit 63 match? bit 63 match? DS1986 t x serial number 6 bytes DS1986 t x crc byte n nn y y y nn y n n y y y DS1986 t x bit 0 DS1986 t x bit 0 DS1986 t x bit 1 DS1986 t x bit 1 DS1986 t x bit 63 DS1986 t x bit 63 master t x bit 1 master t x bit 0 master t x bit 0 master t x bit 1 master t x bit 63 master t x bit 63 master t x reset pulse master t x rom function command n n from memory functions flow chart (figure 5) short reset pulse? od=0 n y to memory functions flow chart (figure 5) 1) to be transmitted or received at overdrive speed if od=1 2) the presence pulse will be short if od=1 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 2) 1) from figure 8 second part to figure 8 second part to figure 8 second part from figure 8, second part DS1986 052298 16/24 rom functions flow chart figure 8
n y y 3ch overdrive skip 69h overdrive match bit 0 match? bit 1 match? bit 63 match? n n n y master t x bit 63 n od=1 od=1 master tx bit 0 master tx bit 1 y 3) always to be transmitted at overdrive speed 3) 3) 3) to figure 8 first part from figure 8 first part from figure 8 first part to figure 8 first part DS1986 052298 17/24 rom functions flow chart figure 8 (cont'd)
DS1986 052298 18/24 overdrive skip rom [3ch] on a singledrop bus this command can save time by allowing the bus master to access the memory functions without providing the 64bit rom code. unlike the normal skip rom command the overdrive skip rom sets the DS1986 in the overdrive mode (od=1). all communica- tion following this command has to occur at overdrive speed until a reset pulse of minimum 480 m s duration resets all devices on the bus to regular speed (od=0). when issued on a multidrop bus this command will set all overdrivecapable devices into overdrive mode. to subsequently address a specific overdrivecapable device, a reset pulse at overdrive speed has to be issued followed by a match rom or search rom com- mand sequence. this will shorten the time for the search process. if more than one slave supporting overdrive is present on the bus and the overdrive skip rom command is followed by a read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wireand result). overdrive match rom [69h] the overdrive match rom command, followed by a 64bit rom sequence transmitted at overdrive speed, allows the bus master to address a specific DS1986 on a multidrop bus and to simultaneously set it in overdrive mode. only the DS1986 that exactly matches the 64bit rom sequence will respond to the subsequent memory function command. slaves already in overdrive mode from a previous overdrive skip or match command will remain in overdrive mode. all other slaves that do not match the 64bit rom sequence or do not support overdrive will return to or remain at regular speed and wait for a reset pulse of minimum 480 m s duration. the overdrive match rom command can be used with a single or multiple devices on the bus. 1wire signalling the DS1986 requires strict protocols to insure data integrity. the protocol consists of five types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, read data and pro- gram pulse. all these signals except presence pulse are initiated by the bus master. the DS1986 can communi- cate at two different speeds, regular speed and over- drive speed. if not explicitly set into the overdrive mode, the DS1986 will communicate at regular speed. while in overdrive mode the fast timing applies to all commu- nicationrelated wave forms. the initialization sequence required to begin any com- munication with the DS1986 is shown in figure 9. a reset pulse followed by a presence pulse indicates the DS1986 is ready to accept a rom command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 m s at regular speed, 48 m s at overdrive speed). the bus master then releases the line and goes into receive mode (rx). the 1wire bus is pulled to a high state via the pullup resistor. after detecting the rising edge on the data pin, the DS1986 waits (t pdh , 1560 m s at regu- lar speed, 26 m s at overdrive speed) and then transmits the presence pulse (t pdl , 60240 m s at regular speed, 824 m s at overdrive speed). a reset pulse of 480 m s or longer will exit the overdrive mode returning the device to regular speed. if the DS1986 is in overdrive mode and the reset pulse is no longer than 80 m s the device will remain in overdrive mode. read/write time slots the definitions of write and read time slots are illustrated in figure 10. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the DS1986 to the master by triggering a delay circuit in the DS1986. during write time slots, the delay circuit determines when the DS1986 will sample the data line. for a read data time slot, if a a0o is to be transmitted, the delay circuit determines how long the DS1986 will hold the data line low overriding the 1 gen- erated by the master. if the data bit is a a1o, the i button will leave the read data time slot unchanged. program pulse to copy data from the 8bit scratchpad to the eprom data or status memory, a program pulse of 12 volts is applied to the data line after the bus master has con- firmed that the crc for the current byte is correct. dur- ing programming, the bus master controls the transition from a state where the data line is idling high via the pullup resistor to a state where the data line is actively driven to a programming voltage of 12 volts providing a minimum of 10 ma of current to the DS1986. this pro- gramming voltage (figure 11) should be applied for 480 m s, after which the bus master returns the data line to an idle high state controlled by the pullup resistor. note that due to the high voltage programming requirements for any 1wire eprom device, it is not possible to mul- tidrop noneprom based 1wire devices with the DS1986 during programming. an internal diode within the noneprom based 1wire devices will attempt to clamp the data line at approximately 8 volts and could potentially damage these devices.
DS1986 052298 19/24 initialization procedure areset and presence pulseso figure 9 t rsth t rstl t r v pullup v pullup min v ih min v il max 0v t pdh t pdl resistor master DS1986 master r x apresence pulseo master t x areset pulseo regular speed 480 m s < t rstl < * 480 m s < t rsth < (includes recovery time) 15 m s < t pdh < 60 m s 60 m s < t pdl < 240 m s overdrive speed 48 m s < t rstl < 80 m s 48 m s < t rsth < 2 m s < t pdh < 6 m s 8 m s < t pdl < 24 m s * in order not to mask interrupt signalling by other devices on the 1wire bus, t rstl + t r should always be less than 960 m s. read/write timing diagram figure 10 writeone time slot 60 m s t rec t low1 v pullup v pullup min v ih min v il max 0v 15 m s DS1986 sampling window t slot resistor master DS1986 regular speed 60 m s < t slot < 120 m s 1 m s < t low1 < 15 m s 1 m s < t rec < overdrive speed 6 m s < t slot < 16 m s 1 m s < t low1 < 2 m s 1 m s < t rec < (od: 2 m s) (od: 6 m s)
DS1986 052298 20/24 read/write timing diagram (cont'd) figure 10 writezero time slot v pullup v pullup min v ih min v il max 0v t slot t rec t low0 DS1986 sampling window 60 m s 15 m s (od: 2 m s) (od: 6 m s) regular speed 60 m s < t low0 < t slot < 120 m s 1 m s < t rec < overdrive speed 6 m s < t low0 < t slot < 16 m s 1 m s < t rec < readdata time slot v pullup v pullup min v ih min v il max 0v t slot t rec t rdv t lowr regular speed 60 m s < t slot < 120 m s 1 m s < t lowr < 15 m s 0 < t release < 45 m s 1 m s < t rec < t rdv = 15 m s t su < 1 m s t release master sampling window resistor master DS1986 overdrive speed 6 m s < t slot < 16 m s 1 m s < t lowr < 2 m s 0 < t release < 4 m s 1 m s < t rec < t rdv = 2 m s t su < 1 m s t su
DS1986 052298 21/24 program pulse timing diagram figure 11 >5 m s line type legend: v pullup gnd v pp >5 m s 480 m s normal 1wire communication ends normal 1wire communication resumes bus master active high (12v @ 10 ma) t rp t fp t dp t dv resistor pullup t pp crc generation with the DS1986 there are two different types of crcs (cyclic redundancy checks). one crc is a 8bit type and is stored in the most significant byte of the 64bit rom. the bus master can compute a crc value from the first 56 bits of the 64bit rom and compare it to the value stored within the DS1986 to determine if the rom data has been received errorfree by the bus master. the equivalent polynomial function of this crc is: x 8 + x 5 + x 4 + 1. this 8bit crc is received in the true (non inverted) form when reading the rom of the DS1986. it is computed once at the factory and lasered into the rom. the other crc is a 16bit type, generated according to the standardized crc16polynomial function x 16 + x 15 + x 2 + 1. this crc is used to safeguard userdefined eprom data when reading data memory or status memory. it is the same type of crc as is used with nvram based i buttons to safeguard data packets of the i button file structure. in contrast to the 8bit crc, the 16bit crc is always returned in the complemented (inverted) form. a crcgenerator inside the DS1986 chip (figure 12) will calculate a new 16bit crc at every situation shown in the command flow chart of figure 5. the DS1986 provides this crcvalue to the bus mas- ter to validate the transfer of command, address, and data to and from the bus master. when reading the data memory of the DS1986 with the read memory com- mand, the 16bit crc is only transmitted as the end of the memory is reached. this crc is generated by clear- ing the crc generator, shifting in the command, low address, high address and every data byte starting at the first addressed memory location and continuing until the end of the implemented data memory is reached. when reading the status memory with the read status command, the 16bit crc is transmitted when the end of each 8byte page of the status memory is reached. at the initial pass through the read status flow chart the 16bit crc will be generated by clearing the crc gen- erator, shifting in the command byte, low address, high address and the data bytes beginning at the first addressed memory location and continuing until the last byte of the addressed eprom status data page is reached. subsequent passes through the read status flow chart will generate a 16bit crc that is the result of clearing the crc generator and then shifting in the new data bytes starting at the first byte of the next page of the eprom status data field and continuing until the last byte of the page is reached. when reading the data memory of the DS1986 with the extended read memory command, there are two situa- tions where a 16bit crc is transmitted. one 16bit crc follows each redirection byte, another 16bit crc is received after the last byte of a memory data page is read. the crc at the end of the memory page is always the result of clearing the crc generator and shifting in the data bytes beginning at the first addressed memory location of the eprom data page until the last byte of this page. with the initial pass through the extended read memory flow chart the 16bit crc value is the result of shifting the command byte into the cleared crc generator, followed by the two address bytes and the redirection byte. subsequent passes through the extended read memory flow chart will gen-
DS1986 052298 22/24 erate a 16bit crc that is the result of clearing the crc generator and then shifting in the redirection byte only. when writing to the DS1986 (either data memory or sta- tus memory), the bus master receives a 16bit crc to verify the correctness of the data transfer before apply- ing the programming pulse. with the initial pass through the write memory/status flow chart the 16bit crc will be generated by clearing the crcgenerator, shifting in the command, address low, address high and the data byte. subsequent passes through the write memory/ status flow chart due to the DS1986 automatically incre- menting its address counter will generate an 16bit crc that is the result of loading (not shifting) the new (incremented) address into the crc generator and then shifting in the new data byte. the comparison of crc values and decision to con- tinue with an operation are determined entirely by the bus master. there is no circuitry on the DS1986 that pre- vents a command sequence from proceeding if the crc stored in or calculated by the DS1986 does not match the value generated by the bus master. for more details on generating crc values including example imple- mentations in both hardware and software, see the book of ds19xx i button standards. crc16 hardware description and polynomial figure 12 1st stage 2nd stage 3rd stage 4th stage 5th stage 6th stage 7th stage 8th stage x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 polynomial = x 16 + x 15 + x 2 + 1 9th stage 10th stage 11th stage 12th stage 13th stage 14th stage 15th stage 16th stage x 9 x 10 x 11 x 12 x 13 x 14 x 15 input data x 16 crc output
DS1986 052298 23/24 absolute maximum ratings* voltage on any pin relative to ground 0.5v to +12.0v operating temperature 40 c to +85 c storage temperature 55 c to +125 c * this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operation sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (v pup =2.8v to 6.0v; 40 c to +85 c) parameter symbol min typ max units notes logic 1 v ih 2.2 v 1, 6 logic 0 v il -0.3 +0.8 v 1, 10 output logic low @ 4 ma v ol 0.4 v 1 output logic high v oh v pup 6.0 v 1, 2 input load current i l 5 m a 3 operating charge q op 30 nc 7, 8 programming voltage @ 10 ma v pp 11.5 12.0 v capacitance (t a = 25 c) parameter symbol min typ max units notes data (1wire) c in/out 800 pf 9 ac electrical characteristics regular speed (v pup =2.8v to 6.0v; 40 c to +85 c) parameter symbol min typ max units notes time slot t slot 60 120 m s write 1 low time t low1 1 15 m s write 0 low time t low0 60 120 m s read data valid t rdv exactly 15 m s release time t release 0 15 45 m s read data setup t su 1 m s 5 recovery time t rec 1 m s reset time high t rsth 480 m s 4 reset time low t rstl 480 m s presence detect high t pdhigh 15 60 m s presence detect low t pdlow 60 240 m s delay to program t dp 5 m s delay to verify t dv 5 m s program pulse width t pp 480 m s program voltage rise time t rp 0.5 5.0 m s program voltage fall time t fp 0.5 5.0 m s
DS1986 052298 24/24 ac electrical characteristics overdrive speed (v pup =2.8v to 6.0v; 40 c to 70 c) parameter symbol min typ max units notes time slot t slot 6 16 m s write 1 low time t low1 1 2 m s write 0 low time t low0 6 16 m s read data valid t rdv exactly 2 m s release time t release 0 1.5 4 m s read data setup t su 1 m s 5 recovery time t rec 1 m s reset time high t rsth 48 m s 4 reset time low t rstl 48 80 m s presence detect high t pdhigh 2 6 m s presence detect low t pdlow 8 24 m s notes: 1. all voltages are referenced to ground. 2. v pup = external pullup voltage. 3. input load is to ground. 4. an additional reset or communication sequence cannot begin until the reset high time has expired. 5. read data setup time refers to the time the host must pull the 1wire bus low to read a bit. data is guaranteed to be valid within 1 m s of this falling edge. 6. v ih is a function of the external pullup resistor and v pup . 7. 30 nanocoulombs per 72 time slots @ 5.0v. 8. at v cc =5.0v with a 5k w pullup to v cc and a maximum time slot of 120 m s. 9. capacitance on the data pin could be 800 pf when power is first applied. if a 5k w resistor is used to pull up the data line to v cc , 5 m s after power has been applied the parasite capacitance will not affect normal communica- tions. 10. under certain low voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse.

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